Virtually all large scale integrated circuits are now designed in detail by means of a computerized design tool, that is to say a data processor which is loaded with a program (usually called a `compiler`). A circuit designer provides input data representing, usually in architecturally independent form, a specification of a circuit which is to be ultimately realized in the form of an integrated circuit. The input data generally represents a circuit in a high level schematic form; a display device employing icons representing basic data processing functions may be manipulated on a display screen and an associated program may convert the icon representation into data defining the high level specification in an appropriate machine language. The computerized design tool or machine converts, in accordance with established practice, the high level specification into a netlist, which defines the integrated circuit in terms of basic circuits or cells and their interconnections. Methods exist for the conversion of the netlist by automatic data processing into masks employed in the fabrication of the integrated circuit.
Established methods of design include automatic optimization procedures by means of which circuits can be rendered in a form which is better adapted for fabrication, or rearranged to improve throughput or speed of operation of the final integrated circuit. Other established methods include the modification of a provisional netlist into a revised form, generally for the same purposes of improving performance, or reducing the area occupied by the integrated circuit.
In order to facilitate the design of very large scale integrated circuits, modern methods of automatic synthesis employ a cell library. This is, in practical form, stored data representing the structure and a variety of operational parameters of each of a large number of basic circuit elements, such as AND gates, OR gates, inverters, flip-flops and suchlike, which will be used in large numbers in any integrated circuit. As noted in for example Kobayashi et al., U.S. Pat. No. 4922432 issued 1 May 1990, the use of a cell library greatly facilitates the automated design process. In particular, the functional, architecture independent, specification of the desired circuit is translated, by the machine, into an architecture specific, structural level definition of an integrated circuit. The data representing the structural level definition includes a list of the integrated circuit hardware cells needed to achieve the hardware specifications. These cells are selected, by the machine, from a cell library of previously designed hardware cells of various functions and specification. The machine also generates data paths interconnecting the selected hardware cells. The selected hardware cells and their interconnections constitute the netlist from which, as is noted above, it is possible to employ existing layout systems to generate the chip level masked data required to produce the integrated circuit in chip form.
An important aspect of the use of a cell library is its development, i.e. the conversion of the data representing the various hardware elements and their parameters into a different form. One reason for so doing is to render the cells better adapted for use in simulators or in optimization of netlists.
The compilation of a cell library is a formidable and lengthy task and its development hardly less so. Each hardware cell has to be modelled, beth in respect of its function and in respect of its detailed performance. As noted by, for example, Westhoff in Electronic Design Automation 1988, pages 33-47, up to fifty primitives may be required to model all the pin-to-pin delay paths and timing checks within a single D flip-flop.
It is known to employ automatic computation in library development, particularly to obtain timing data by means of simulations of the transistor-level behaviour of the cells, as described by J. Dressen, `Standard Cell Development Flow`, Euro-Asic 90, pages 450-455.
An important set of data characterizing a circuit element is its truth table, which can be a fast and accurate model of the logical behaviour of the cell and can also be a reference for development of the cell library. Indeed, during the simulation of cells described in terms of hardware language the output values of the cells have to be computed whereas if a truth table model were employed these values need only be read in the output fields of the truth table.